Phase change memory points comprise of a material which can change physical state under the effect of an electric signal, and more precisely under the effect of a temperature rise caused by a voltage and an electric current (Joule effect). This state change is remanent and comes with a change in the electrical properties of the memory point. In a first so-called amorphous phase, the material has a high electrical resistivity, and in a second so-called crystalline phase the material has a low electrical resistivity.
Progress made in the compositions of phase change materials, for example chemical element-based alloys in column VI of the Mendeleyev table, such as tellurium Te or selenium Se, are such that the phase change can be obtained with a voltage of a few volts and a current of a few hundred microamperes only, which enables phase change memory points to be integrated into the memories implanted onto semiconductor chips.
As an example, FIG. 1 represents the architecture of a memory array MA of the type described by EP 1 450 373. The memory array MA comprises memory cells CELi,j,k arranged as a matrix and each linked to a word line WLi of rank i and to a bit line BLjk of rank j (j ranging from 0 to m) belonging to a column COLk of rank k. Each memory cell CELi,j,k comprises a selection switch TS, for example an NMOS transistor, and a phase change memory point P. The anode of the memory point P is linked to a bit line BLjk and its cathode is linked through the transistor TS to a low potential or to a line switchable to a low potential, for example the ground. The gate terminal of the transistor TS is linked to a word line WLi.
As shown in FIG. 2, the memory point P has two stable states SET and RST (short for “RESET”) corresponding to the two abovementioned types of resistivity. In the state SET which corresponds for example to the storing of a logic “1”, the memory point has a first series resistance, for example 5 to 10 K ohms, while in the state RST corresponding to the storing of a logic “0”, the memory point has a second series resistance, for example 100 to 200 K ohms.
By analogy with electrically erasable and programmable memories using floating-gate transistors, the state SET will be called “programmed state” and the state RST will be called “erased state”. The change from the programmed state to the erased state is ensured by applying to the memory point a pulse RPULSE of the type represented in FIG. 3B, having a plateau of a duration tRST of a few dozen nanoseconds, for example 100 nanoseconds, and a quench time Tq1 (“Tquench”) as fast as possible, which does not in practice exceed a few nanoseconds. The pulse RPULSE is voltage- or current-controlled and has a maximal voltage Vp of a few volts and a maximal current Ip of a few hundred microamperes, which cause a warming by Joule effect rendering the material amorphous.
The change from the erased state to the programmed state is ensured by applying to the memory point a pulse SPULSE of the type represented in FIG. 3B, of a duration tSET. The pulse has a plateau of a few dozen nanoseconds, for example 50 nanoseconds, and a quench time Tq2 that is quite long, for example 300 nanoseconds. Thus the pulse SPULSE has a decreasing ramp from an instant tRAMP calculated as of the instant to of it being sent, the duration of the ramp being equal to tSET-tRAMP. The pulse SPULSE is also voltage- or current-controlled and has a maximal voltage Vp of a few volts and a maximal current Ip of a few hundred microamperes, followed by the decreasing voltage or current ramp the effect of which is to recrystallize the material.
In summary, the quench time Tq2 of the pulse SPULSE is quite long while on the contrary the quench time Tq1 of the pulse RPULSE is very short to prevent the recrystallization.
Reading the memory point P then makes it possible to determine whether the latter has the first or the second series resistance, and a binary value 1 or 0 is associated with the resistance value read. Such a reading is generally done under a low voltage so as not to modify the state of the memory point by causing spurious erasing or programming. A low-value read voltage, for example 0.5 V, is sufficient to read the memory point while being sufficiently low so as not to cause a change in the programmed or erased state of the memory point.
The integration of phase change memory points into a memory produced on a semiconductor substrate is an objective for this memory technology to be industrially used, due to the low cost price of the integrated circuits. For this purpose, the means for controlling the memory cells, mainly the erase and programming means, are produced in a rational and inexpensive manner and little cumbersome in terms of semiconductor surface.
For a better understanding of the erase and programming solutions provided in prior art, FIG. 4 represents a classic architecture of phase change memory of the type described by the application EP 1 450 373. The memory represented comprises a memory array MA and memory cells of the type described above. The memory also comprises a column selection circuit CSEL1 connected to the bit lines BL (BL0k, . . . BLjk, . . . BLmk). The selection circuit CSEL1 comprises bit line (BK0k, . . . BKjk, . . . BKmk) selection blocks BK with one block per bit line. Each selection block BK comprises PMOS-type transistors TP1, TP2 and an NMOS-type transistor TN1 in series. These transistors are controlled by selection signals YMk, YNk, YOk supplied by a column decoder CDEC1.
During memory cell erasing or programming phases, the pulses RPULSE or SPULSE are supplied by writing circuits WRCT (WRCT0, . . . WRCTj, . . . WRCTm). The pulses RPULSE or SPULSE are applied to the bit lines through isolation transistors TIW, a multiplexing bus BMUX and the selection blocks BK. For this purpose, the isolation transistors TIW are put into the on state by a gate signal YW, the signals YM and YN are set to 0 (ground of the circuit) and the signal YO is taken to a gate voltage of high value so that the voltage Vp or the current Ip is transferred without loss. Simultaneously, a row decoder RDEC applies to a word line WLi a selection signal SWLi which biases the gates of the selection transistors TS for selecting the memory cells connected to this word line, and puts these transistors into the on state.
This erasing/programming method has the disadvantage of being relatively complex to implement. In particular, the writing circuits WRCT are complex to produce because the profile and the duration of the pulses RPULSE or SPULSE must be controlled with great precision, in particular the quench times Tq1 and Tq2.